In general, hardware and software co-simulation is defined as the ability to execute target microprocessor software within a simulated hardware environment for the purpose of analyzing, debugging and implementing the hardware and the software. In general, hardware and software co-simulation reduces a product's time-to-market, reduces the cost of the product (as co-simulation can eliminate multiple manufacturing builds) and allows software development prior to hardware availability. Currently, hardware and software co-simulations are accomplished through the use of functional models, timed functional simulation models, instruction-set simulation models and/or cycle accurate simulation models. When functional models are utilized to co-simulate hardware and software, the hardware and software are typically described in a high-level language, e.g., C, or with visual tools that execute on a general purpose computing platform. In general, functional models contain little or no timing information associated with the hardware and/or software execution.
With timed functional simulation models, the hardware executes on a scheduled interval, typically with respect to a clock, and the software may be synchronized with the hardware model at discrete time intervals. In general, the application software for the timed functional simulation model executes directly on a host computer system. The timed functional model has the advantage of fast simulation and less computations, but with an overall reduced fidelity and accuracy of the hardware/software simulation. In the instruction set simulation model, the application software is cross-compiled to a target processor instruction set, which is emulated on the host computer system, which acts as an instruction set simulator. In this manner, the instruction set simulator executes in synchronization, on instruction boundaries, with the hardware model.
In the cycle accurate simulation model, the application software is cross-compiled to a target processor instruction set and the instructions are executed on a cycle-by-cycle basis in synchronization with a scheduled hardware model. The cycle accurate simulation model and the instruction set simulation model are often referred to as co-verification models.
A prior technique for implementing a timed functional simulation model, which is described in U.S. Pat. No. 6,230,114, includes an analysis step that adds timing information to the application software to achieve a relatively high fidelity model. In this timed functional simulation model, synchronization points are inserted at each linear block of code. These synchronization points account for target processor instruction timing and pipeline effects and provide a highly accurate simulation model, whose accuracy approaches that of the final system, without performing continual context switching. However, this timed functional simulation model, in general, provides greater accuracy than required during software analysis, design and prototyping stages. The timed functional simulation model also does not allow for the adjustment of timing synchronization points to aid in exploration of target software execution times.
What is needed is a hardware and software co-simulation technique that facilitates exploration of different architectures and provides acceptable accuracy, while simultaneously reducing co-simulation time.